The present invention relates to methods for forming a multilayer interconnect in which a lower layer interconnect and an upper layer interconnect are connected through a via contact and methods for checking the same, and more particularly relates to a method for forming using a dual damascene process a multilayer interconnect in which a via contact and an upper layer interconnect are formed of a conductive material by filling the material into layers.
Conventionally, as a high-density interconnect used for a semiconductor integrated circuit or the like, multilayer interconnects in which a lower layer interconnect and an upper layer interconnect are connected through a via contact have been used. A dual damascene process in which a multilayer interconnect is simultaneously formed by filling a material into layers to form a via contact and an upper layer interconnect above a lower layer interconnect is one of known techniques for forming such a multilayer interconnect.
Hereinafter, a method for forming a multilayer interconnect using a known dual damascene process will be described with reference to the accompanying drawings.
FIGS. 5A through 5C, FIGS. 6A and 6B, and FIGS. 7A and 7B are cross-sectional views illustrating respective process steps for forming a known multilayer interconnect.
First, as shown in FIG. 5A, on a semiconductor substrate 101 including integrated circuit elements, a first interlevel insulating film 102 is formed, an opening to be a lower layer interconnect forming region is formed by photolithography and dry etching, and then copper is deposited in a lower layer interconnect forming region by sputtering or metal plating. Thereafter, the substrate is polished by chemical mechanical polishing (CMP) until the first interlevel insulating film 102 is exposed. In this manner, a lower layer interconnect 103 of copper is formed in an upper part of the first interlevel film 102.
Next, as shown in FIG. 5B, an etching stopper layer 104 of silicon nitride and a second interlevel insulating film 105 of silicon oxide are deposited on the substrate in this order by plasma chemical vapor deposition (plasma CVD).
Subsequently, a first reflection-prevention film 106 of an organic material is formed on the second interlevel insulating film 105 by spin coating.
Next, as shown in FIG. 5C, a first resist pattern 107 is formed by photolithography, and then the first reflection-prevention film 106 and the second interlevel insulating film 105 are etched in this order by dry etching using the first resist pattern 107 as a mask. In this manner, an aperture 105a is formed in the second interlevel insulating film 105.
Next, as shown in FIG. 6A, the first resist pattern 107 and the first reflection-prevention film 106 are removed in this order by ashing, and then the surfaces of the second interlevel insulating film 105 are cleaned. Thereafter, the second reflection-prevention film 108 of an organic material is formed by spin coating so as to fill the aperture 105a. 
Next, as shown in FIG. 6B, a second resist pattern 109 is formed by photolithography, and then the second reflection-prevention film 108 and the second interlevel insulating film 105 are patterned in this order by dry etching using the second resist pattern 109 as a mask. In this manner, an interconnect groove 105b is formed.
In this dry etching, an etching rate for the second reflection-prevention film 108 filled in the aperture 105a is lower than that for the second interlevel insulating film 105. Therefore, the lower layer interconnect 103 and the etching stopper layer 104 which are located under the aperture 105a are protected by the second reflection-prevention film 108 filled in the aperture 105a from damages caused during the formation of the interconnect groove 105b. 
In this case, when the interconnect groove 105b is formed, part of the second interlevel insulating film 105 which is in contact with the second reflection-prevention film 108 may not be removed and thus a etching residue having a projecting shape i.e., a crown fence 105c may be generated around the aperture 105a of the interconnect groove 105b. 
Next, as shown in FIG. 7A, the second reflection-prevention film 108 and the second resist pattern 109 are removed by ashing, and then the surfaces of the second interlevel insulating film 105 are cleaned. Thereafter, part of the etching stopper layer 104 exposed at the bottom of the aperture 105a is removed by dry etching using the second interlevel insulating film 105 so that the lower layer interconnect 103 is exposed. In this manner, a via hole is formed so as to pass through the etching stopper layer 104 and the second interlevel insulating film 105 and reach the lower layer interconnect 103.
Next, as shown in FIG. 7B, a metal film 110 of copper is deposited on the second interlevel insulating film 105 by sputtering or metal plating so as to fill the aperture 105a and the interconnect groove 105b. Thereafter, copper is polished by CMP until the second interlevel insulating film 105 is exposed. In this manner, a multilayer interconnect in which part of the metal film 110 located in the aperture 105a to be a via contact 110a and part of the metal film 110 located in the interconnect groove 105b to be an upper layer interconnect 110b is formed.
Moreover, as an attempt to prevent the generation of the grown fence 105c in a first known example shown in FIG. 6B, a method for fabricating a semiconductor device in which an organic film is formed in a lower portion of an aperture 105a and then an interconnect groove is formed is well known.
Hereinafter, a method for forming a multilayer interconnect as a second known example in which an organic film is formed in a lower portion of the aperture 105a and then an interconnect groove is formed will be described with reference to the accompanying drawings.
FIGS. 8A and 8B are cross-sectional views illustrating respective process steps for forming a multilayer interconnect in the second known example. Note that in FIG. 8, each member also shown in the first known example is identified by the same reference numeral and therefore description thereof will be omitted.
In the second known example, an aperture 105a is first formed in an second interlevel insulating film 105 in the same process steps of the first known example shown in FIGS. 5A through 5C.
Next, as shown in FIG. 8A, a first resist pattern 107 is removed and then the surfaces of the second interlevel insulating film 105 are cleaned. Thereafter, an organic material is applied over a first refection-prevention film 106 by spin coating so as to fill the aperture 105a. Then, the entire upper surface of the substrate is etched to form an organic film 111 of the organic material at the bottom of the aperture 105a. In this case, the organic film 111 protects a lower layer interconnect 103 from damages caused by etching in the process step forming an interconnect groove 105b to be performed next.
Next, as shown in FIG. 8B, an interconnect 105b is formed by dry etching using a second resist pattern 109 as a mask.
Thereafter, in the same process steps shown in FIGS. 7A and 7B, copper is deposited on the aperture 105a and the interconnect 105b, thereby forming a multilayer interconnect.
In the second known example, an organic material film is not filled in an upper portion of the aperture 105a which is to be an interconnect groove 105b forming region, and thus the interconnect groove 105b can be formed without any crown fence generated.
However, in the method for forming a multilayer interconnect according to the first known example, in the process step of forming an interconnect groove 105b, an organic material is filled in the aperture 105a in order to protect the lower layer interconnect 103 from damages caused by etching. Thus, a crown fence 105c is generated in part of the interconnect groove 105b which is in contact with the aperture 105a. Therefore, resist between an upper layer interconnect 110b and a via contact 110a is increased. Furthermore, the upper layer interconnect 110b and the via contact 110a may be electrically separated depending on the size of the crown fence 105c. As has been described, in the method for forming a multilayer interconnect of the first known example, the reliability of a multilayer interconnect as well as the yield thereof is reduced.
In contrast, when the interconnect groove 110b is formed without causing the generation of a crown fence using the method for forming a multilayer interconnect of the second known example, the number of process steps is increased, resulting in increased production costs.
Moreover, in the first and second known examples, in the process step of removing the part of an etching stopper layer 104 located under the aperture 105a to form a via hole, the part of the lower layer interconnect 103 exposed at the surface of the substrate is corroded by a plasma gas during etching. Therefore, the reliability of a multilayer interconnect is reduced.